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ArGen
ArGen
Commits
b8e03afa
Commit
b8e03afa
authored
Mar 09, 2021
by
Théotime BOLLENGIER
Browse files
signature
parent
a356316d
Changes
1
Hide whitespace changes
Inline
Side-by-side
lib/argen/hdl_arch_writer.rb
View file @
b8e03afa
...
...
@@ -114,25 +114,52 @@ module ArGen
update_IOs_position
()
@wrapper_signautre
=
[
if
@wrapperWithDMA
then
@wrapperDmaWordWidth
.
to_s
(
2
).
rjust
(
6
,
'0'
)
else
'000000'
end
,
if
@wrapperWithMemAccess
then
@wrapperMemWordWidth
.
to_s
(
2
).
rjust
(
6
,
'0'
)
else
'000000'
end
,
if
@wrapperWithMemAccess
then
@wrapperMemAddrWidth
.
to_s
(
2
).
rjust
(
6
,
'0'
)
else
'000000'
end
,
if
@wrapperWithDMA
then
'1'
else
'0'
end
,
if
@wrapperWithMemAccess
then
'1'
else
'0'
end
,
if
@wrapperWithInterrupt
then
'1'
else
'0'
end
,
(
@wrapper_archFileSHA1
&
0x7ff
).
to_s
(
2
).
rjust
(
11
,
'0'
),
(
@bitstream_size
+
(
@withIOReorderingRing
?
(
Math
.
log2
(
@vFpgaNbIoPins
+
1
).
ceil
*
@vFpgaNbIoPins
*
2
)
:
0
)).
to_s
(
2
).
rjust
(
23
,
'0'
),
@vFpgaNbIoPins
.
to_s
(
2
).
rjust
(
9
,
'0'
),
(
@archParams
[
:layoutWidth
]).
to_s
(
2
).
rjust
(
7
,
'0'
),
(
@archParams
[
:layoutHeight
]).
to_s
(
2
).
rjust
(
7
,
'0'
),
(
@archParams
[
:routChanWidth
]).
to_s
(
2
).
rjust
(
6
,
'0'
),
@clbs
[
0
].
nbBLEs
.
to_s
(
2
).
rjust
(
4
,
'0'
),
@clbs
[
0
].
nbInputs
.
to_s
(
2
).
rjust
(
4
,
'0'
),
@clbs
[
0
].
k
.
to_s
(
2
).
rjust
(
4
,
'0'
)
# PRES1
[
(
@archParams
[
:layoutWidth
]
-
1
).
to_s
(
2
).
rjust
(
6
,
'0'
)[
-
6
..-
1
],
(
@archParams
[
:layoutHeight
]
-
1
).
to_s
(
2
).
rjust
(
6
,
'0'
)[
-
6
..-
1
],
(
@archParams
[
:routChanWidth
]
-
1
).
to_s
(
2
).
rjust
(
6
,
'0'
)[
-
6
..-
1
],
(
@clbs
[
0
].
nbBLEs
-
1
).
to_s
(
2
).
rjust
(
4
,
'0'
)[
-
4
..-
1
],
(
@clbs
[
0
].
nbInputs
-
1
).
to_s
(
2
).
rjust
(
7
,
'0'
)[
-
7
..-
1
],
(
@clbs
[
0
].
k
-
1
).
to_s
(
2
).
rjust
(
3
,
'0'
)[
-
3
..-
1
]
].
reverse
.
join
,
# PRES2
[
(
@bitstream_size
+
(
@withIOReorderingRing
?
(
Math
.
log2
(
@vFpgaNbIoPins
+
1
).
ceil
*
@vFpgaNbIoPins
*
2
)
:
0
)).
to_s
(
2
).
rjust
(
23
,
'0'
)[
-
23
..-
1
],
@vFpgaNbIoPins
.
to_s
(
2
).
rjust
(
9
,
'0'
)[
-
9
..-
1
]
].
reverse
.
join
,
# PRES3
[
if
@wrapperWithDMA
then
@wrapperDmaWordWidth
.
to_s
(
2
).
rjust
(
6
,
'0'
)[
-
6
..-
1
]
else
'000000'
end
,
if
@wrapperWithMemAccess
then
@wrapperMemWordWidth
.
to_s
(
2
).
rjust
(
6
,
'0'
)[
-
6
..-
1
]
else
'000000'
end
,
if
@wrapperWithMemAccess
then
@wrapperMemAddrWidth
.
to_s
(
2
).
rjust
(
6
,
'0'
)[
-
6
..-
1
]
else
'000000'
end
,
if
@wrapperWithDMA
then
'1'
else
'0'
end
,
if
@wrapperWithMemAccess
then
'1'
else
'0'
end
,
if
@wrapperWithInterrupt
then
'1'
else
'0'
end
,
(
@wrapper_archFileSHA1
&
0x7ff
).
to_s
(
2
).
rjust
(
11
,
'0'
)[
-
11
..-
1
]
].
reverse
.
join
].
reverse
.
join
.
to_i
(
2
).
to_s
(
16
).
rjust
(
24
,
'0'
)
# if @wrapperWithDMA then @wrapperDmaWordWidth.to_s(2).rjust(6,'0') else '000000' end,
# if @wrapperWithMemAccess then @wrapperMemWordWidth.to_s(2).rjust(6,'0') else '000000' end,
# if @wrapperWithMemAccess then @wrapperMemAddrWidth.to_s(2).rjust(6,'0') else '000000' end,
# if @wrapperWithDMA then '1' else '0' end,
# if @wrapperWithMemAccess then '1' else '0' end,
# if @wrapperWithInterrupt then '1' else '0' end,
# (@wrapper_archFileSHA1 & 0x7ff).to_s(2).rjust(11,'0'),
#
# (@bitstream_size + (@withIOReorderingRing ? (Math.log2(@vFpgaNbIoPins + 1).ceil*@vFpgaNbIoPins*2) : 0)).to_s(2).rjust(23,'0'),
# @vFpgaNbIoPins.to_s(2).rjust(9,'0'),
#
# (@archParams[:layoutWidth]).to_s(2).rjust(7,'0'),
# (@archParams[:layoutHeight]).to_s(2).rjust(7,'0'),
# (@archParams[:routChanWidth]).to_s(2).rjust(6,'0'),
# @clbs[0].nbBLEs.to_s(2).rjust(4,'0'),
# @clbs[0].nbInputs.to_s(2).rjust(4,'0'),
# @clbs[0].k.to_s(2).rjust(4,'0')
# ].reverse.join.to_i(2).to_s(16).rjust(24,'0')
return
@wrapper_signautre
end
...
...
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