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The ArGen FPGA overlay framework
Python ROS node to handle data recording (to be tested against using rosbags).
Driver for the Blueprint Subsea Seatrac USBL.
Test of initial GitLab for UE 32 Discovery
Projet d'informatique du semestre 2
Démonstration du FPGA ELNATH conçu et réalisé à l'ENSTA-Bretagne.
Example programs to solve questions 1 to 9 of low level control labs
Timings (delays) are reduced (e.g. 5 seconds to 0.5 seconds) to test the code remotely via Internet
List of books and other references for the students according to the RAN of ANO option of ENSTA Bretagne.
PRESENT block cipher with AXI lite interface
A ruby gem to handle and simulate BLIF netlists.