axi_present.vhd 5.62 KB
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library ieee;
use ieee.std_logic_1164.all;
use work.util.all;

entity axi_present is

	generic (
		ADRWIDTH : integer := 8;
		DATAWIDTH : integer := 32
	);
	port (
		-- AXI SLAVE INTERFACE ----------------------------
		-- Clock and Reset
		S_AXI_ACLK : in std_logic;
		S_AXI_ARESETN : in std_logic;
		-- Write Address Channel
		S_AXI_AWADDR : in std_logic_vector(ADRWIDTH - 1 downto 0);
		S_AXI_AWVALID : in std_logic;
		S_AXI_AWREADY : out std_logic;
		S_AXI_AWPROT : in std_logic_vector(2 downto 0); --addr write protection
		-- Write Data Channel
		S_AXI_WDATA : in std_logic_vector(DATAWIDTH - 1 downto 0);
		S_AXI_WSTRB : in std_logic_vector(3 downto 0);
		S_AXI_WVALID : in std_logic;
		S_AXI_WREADY : out std_logic;
		-- Read Address Channel
		S_AXI_ARADDR : in std_logic_vector(ADRWIDTH - 1 downto 0);
		S_AXI_ARVALID : in std_logic;
		S_AXI_ARREADY : out std_logic;
		S_AXI_ARPROT : in std_logic_vector(2 downto 0); --addr read protection
		-- Read Data Channel
		S_AXI_RDATA : out std_logic_vector(DATAWIDTH - 1 downto 0);
		S_AXI_RRESP : out std_logic_vector(1 downto 0);
		S_AXI_RVALID : out std_logic;
		S_AXI_RREADY : in std_logic;
		-- Write Response Channel
		S_AXI_BRESP : out std_logic_vector(1 downto 0);
		S_AXI_BVALID : out std_logic;
		S_AXI_BREADY : in std_logic;
		state_signal : out std_logic_vector (2 downto 0)
	);
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end entity;
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architecture behavioral of axi_present is

	component present_top is
		generic (k : key_enum);
		port (
			plaintext : in std_logic_vector(63 downto 0);
			key : in std_logic_vector(key_bits(k) - 1 downto 0);
			clk : in std_logic;
			reset : in std_logic;
			ciphertext : out std_logic_vector(63 downto 0)
		);
	end component;
	type text_buffer is array (0 to 1) of std_logic_vector(DATAWIDTH - 1 downto 0);
	type key_buffer is array (0 to 3) of std_logic_vector(DATAWIDTH - 1 downto 0);

	signal plaintext_buf : text_buffer;
	signal ciphertext_buf : text_buffer;
	signal key_buf : key_buffer;

	constant plaintext_reads : natural := 2;
	constant key_reads : natural := 4;
	constant active_cycles : natural := 33;
	constant ciphertext_writes : natural := 2;
	signal counter : natural range 0 to 32;
	signal ip_plaintext : std_logic_vector(63 downto 0);
	signal ip_key : std_logic_vector(127 downto 0);
	signal ip_reset : std_logic;
	signal ip_ciphertext : std_logic_vector(63 downto 0);
	type state_type is (idle, read_plaintext, read_key, stabilize, active, write_ciphertext);
	signal state : state_type;
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begin
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	BLOCK_CIPHER : present_top
		generic map(
		k => K_128
		)
		port map(
			plaintext => ip_plaintext, 
			key => ip_key, 
			clk => S_AXI_ACLK, 
			reset => ip_reset, 
			ciphertext => ip_ciphertext
		);

			ip_plaintext <= plaintext_buf(0) & plaintext_buf(1);
			ciphertext_buf (0) <= ip_ciphertext (31 downto 0);
			ciphertext_buf (1) <= ip_ciphertext (63 downto 32);
			ip_key <= key_buf(0) & key_buf(1) & key_buf(2) & key_buf(3);
			ip_reset <= '0' when state = active else '1';
			S_AXI_WREADY <= '1' when (state = read_plaintext or state = read_key) else '0';
			S_AXI_AWREADY <= '1' when (state = read_plaintext or state = read_key) else '0';
			S_AXI_RVALID <= '1' when state = write_ciphertext else '0';
			S_AXI_ARREADY <= '1' when state = write_ciphertext else '0';

			state_machine : process (S_AXI_ACLK)
			begin
				if rising_edge(S_AXI_ACLK) then
					if S_AXI_ARESETN = '0' then
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						state <= idle;
						counter <= 0;
					else
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						case state is
							when idle => 
								ciphertext_buf(0) <= (others => '0');
								ciphertext_buf(1) <= (others => '0');
								S_AXI_RDATA <= (others => '0');
								if S_AXI_WVALID = '1' then
									state <= read_plaintext;
									counter <= 0;
								end if;
 
							when read_plaintext => 
								if S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' then
									plaintext_buf(counter) <= S_AXI_WDATA;
									if counter = plaintext_reads - 1 then
										state <= read_key;
										counter <= 0;
									else
										counter <= counter + 1;
									end if;
								end if;
 
							when read_key => 
								if S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' then
									key_buf(counter) <= S_AXI_WDATA;
									if counter = key_reads - 1 then
										state <= stabilize;
										counter <= 0;
									else
										counter <= counter + 1;
									end if;
								end if;
 
							when stabilize => 
								state <= active;

							when active => 
								if counter = active_cycles - 1 then
									ciphertext_buf(0) <= ip_ciphertext(63 downto 32);
									ciphertext_buf(1) <= ip_ciphertext(31 downto 0);
 
									state <= write_ciphertext;
									counter <= 0;
								else
									counter <= counter + 1;
								end if;
 
							when write_ciphertext => 
								S_AXI_RDATA <= ciphertext_buf (counter);
								if S_AXI_RREADY = '1' then
									if counter = ciphertext_writes - 1 then
										state <= idle;
										counter <= 0;
									else
										counter <= counter + 1;
									end if;
								end if;
						end case;
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					end if;
				end if;
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			end process;
 

			process (state)
				begin
					case state is
						when idle => 
							state_signal <= "000";
						when read_plaintext => 
							state_signal <= "001";
						when read_key => 
							state_signal <= "010";
						when stabilize => 
							state_signal <= "011";
						when active => 
							state_signal <= "100";
						when write_ciphertext => 
							state_signal <= "101";
						when others => 
							state_signal <= "XXX";

					end case;
				end process;


				process (S_AXI_ACLK)
					begin
						if S_AXI_ARESETN = '0' then
							S_AXI_BVALID <= '0';
						else
							S_AXI_BVALID <= '1';
							S_AXI_BRESP <= "00";
							S_AXI_RRESP <= "00";
						end if;
					end process;

end architecture;