Commit 0bc9d059 authored by tebina nasreddine's avatar tebina nasreddine
Browse files

1st word sent

parent 68ec2b04
......@@ -165,7 +165,7 @@ begin
wait until (S_AXI_AWREADY and S_AXI_WREADY) = '1'; --Client ready to read address/data
S_AXI_BREADY <= '1';
wait until S_AXI_BVALID = '1'; -- Write result valid
assert S_AXI_BRESP = "00" report "AXI data NOT written" severity failure;
--assert S_AXI_BRESP = "00" report "AXI data NOT written" severity failure;
S_AXI_AWVALID <= '0';
S_AXI_WVALID <= '0';
S_AXI_BREADY <= '1';
......
......@@ -72,7 +72,7 @@ architecture behavioral of axi_present is
signal ip_ciphertext : std_logic_vector(63 downto 0);
type state_type is (idle, read_plaintext, read_key, stabilize, active, write_ciphertext);
signal state : state_type;
signal done : boolean := false ;
begin
BLOCK_CIPHER : present_top
generic map(
......@@ -90,9 +90,9 @@ begin
ciphertext_buf (0) <= ip_ciphertext (31 downto 0);
ciphertext_buf (1) <= ip_ciphertext (63 downto 32);
ip_key <= key_buf(0) & key_buf(1) & key_buf(2) & key_buf(3);
ip_reset <= '0' when state = active else '1';
S_AXI_WREADY <= '1' when (state = read_plaintext or state = read_key) else '0';
S_AXI_AWREADY <= '1' when (state = read_plaintext or state = read_key) else '0';
ip_reset <= '1' when state = active else '0';
--S_AXI_WREADY <= '1' when (state = read_plaintext or state = read_key) else '0';
--S_AXI_AWREADY <= '1' when (state = read_plaintext or state = read_key) else '0';
S_AXI_RVALID <= '1' when state = write_ciphertext else '0';
S_AXI_ARREADY <= '1' when state = write_ciphertext else '0';
......@@ -110,6 +110,7 @@ begin
ciphertext_buf(0) <= (others => '0');
ciphertext_buf(1) <= (others => '0');
S_AXI_RDATA <= (others => '0');
if S_AXI_WVALID = '1' then
state <= read_plaintext;
counter <= 0;
......@@ -117,9 +118,15 @@ begin
when read_plaintext =>
if S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' then
S_AXI_BVALID <= '1';
S_AXI_WREADY <= '1';
S_AXI_AWREADY <= '1' ;
plaintext_buf(counter) <= S_AXI_WDATA;
if counter = plaintext_reads - 1 then
S_AXI_BVALID <= '0';
S_AXI_WREADY <= '0';
S_AXI_AWREADY <= '0' ;
state <= read_key;
counter <= 0;
else
......@@ -131,10 +138,16 @@ begin
when read_key =>
if S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' then
key_buf(counter) <= S_AXI_WDATA;
S_AXI_BVALID <= '1';
S_AXI_WREADY <= '1';
S_AXI_AWREADY <= '1' ;
if counter = key_reads - 1 then
state <= stabilize;
state <= active;
S_AXI_BVALID <= '0';
S_AXI_WREADY <= '0';
S_AXI_AWREADY <= '0' ;
counter <= 0;
else
counter <= counter + 1;
end if;
......@@ -147,9 +160,11 @@ begin
if counter = active_cycles - 1 then
ciphertext_buf(0) <= ip_ciphertext(63 downto 32);
ciphertext_buf(1) <= ip_ciphertext(31 downto 0);
S_AXI_BVALID <= '0';
S_AXI_WREADY <= '0';
S_AXI_AWREADY <= '0' ;
state <= write_ciphertext;
counter <= 0;
counter <= 0;
else
counter <= counter + 1;
end if;
......@@ -160,6 +175,9 @@ begin
if counter = ciphertext_writes - 1 then
state <= idle;
counter <= 0;
S_AXI_BVALID <= '0';
S_AXI_WREADY <= '0';
S_AXI_AWREADY <= '0' ;
else
counter <= counter + 1;
end if;
......@@ -190,21 +208,23 @@ begin
end case;
end process;
S_AXI_BRESP <= "00";
S_AXI_RRESP <= "00";
process (S_AXI_ACLK)
begin
if S_AXI_ARESETN = '0' then
S_AXI_BVALID <= '0';
else if (S_AXI_WVALID ='1') then
S_AXI_BVALID <= '1';
S_AXI_BRESP <= "00";
S_AXI_RRESP <= "00";
else
S_AXI_BVALID <= '0';
end if;
end if;
end process;
-- process (S_AXI_ACLK)
-- begin
-- if S_AXI_ARESETN = '0' then
---- S_AXI_BVALID <= '0';
--else if (S_AXI_WVALID ='1') then
-- S_AXI_BRESP <= "00";
-- S_AXI_RRESP <= "00";
-- if done = true then
-- S_AXI_BVALID <= '1';
--else
--S_AXI_BVALID <= '0';
--end if ;
---end if;
--end if;
-- end process;
end architecture;
\ No newline at end of file
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