Commit 13f8c5af authored by tebina's avatar tebina
Browse files

...

parent b4d66950
......@@ -96,8 +96,8 @@ begin
ciphertext_buf (1) <= ip_ciphertext (63 downto 32);
ip_key <= key_buf(0) & key_buf(1) & key_buf(2) & key_buf(3);
ip_reset <= '0' when state = active else '1';
S_AXI_BRESP <= "00";
S_AXI_RRESP <= "00";
--S_AXI_BRESP <= "00";
--S_AXI_RRESP <= "00";
ip_plaintext_signal <= ip_plaintext;
ip_ciphertext_buffer <= ciphertext_buf(0);
ip_key_signal <= ip_key;
......@@ -107,6 +107,14 @@ begin
state_machine : process (S_AXI_ACLK)
begin
S_AXI_BVALID <= '0';
S_AXI_BRESP <= (others => '0');
S_AXI_ARREADY <= '0';
S_AXI_RVALID <= '0';
S_AXI_RDATA <= (others => '0');
S_AXI_RRESP <= (others => '0');
S_AXI_AWREADY <= '0';
S_AXI_WREADY <= '0';
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
state <= idle;
......@@ -115,8 +123,8 @@ begin
case state is
when idle =>
S_AXI_RDATA <= (others => '0');
S_AXI_RVALID <= '0';
S_AXI_ARREADY <= '0';
--S_AXI_RVALID <= '0';
--S_AXI_ARREADY <= '0';
S_AXI_BVALID <= '0';
S_AXI_WREADY <= '0';
S_AXI_AWREADY <= '0' ;
......@@ -156,14 +164,16 @@ begin
end case;
when stabilize_read =>
counter <= counter +1 ;
S_AXI_RVALID <= '0';
S_AXI_ARREADY <= '0';
--S_AXI_RVALID <= '0';
--S_AXI_ARREADY <= '0';
state <= write_ciphertext;
if counter = ciphertext_writes-1 then
state <= idle ;
end if;
when active =>
if counter = active_cycles - 1 then
S_AXI_ARREADY <= '1';
S_AXI_RVALID <= '1';
state <= write_ciphertext;
counter <= 0;
else
......@@ -173,8 +183,9 @@ begin
when write_ciphertext =>
--if S_AXI_ARVALID = '1' and S_AXI_RREADY = '1' then
S_AXI_RDATA <= ciphertext_buf(counter);
S_AXI_RVALID <= '1';
S_AXI_ARREADY <= '1';
S_AXI_ARREADY <= '0';
S_AXI_RVALID <= '0';
--S_AXI_ARREADY <= '0';
state <= stabilize_read;
--end if ;
end case;
......@@ -183,6 +194,7 @@ begin
end process;
process (state)
begin
case state is
......
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