Commit 5b9bd617 authored by tebina nasreddine's avatar tebina nasreddine
Browse files

signal debug

parent 7236f888
......@@ -43,11 +43,8 @@ architecture Behavioral of axi_present_tb is
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
state_signal : out std_logic_vector (2 downto 0);
ip_plaintext_signal : out std_logic_vector (63 downto 0);
ip_plaintext_buffer : out std_logic_vector (31 downto 0)
state_signal : out std_logic_vector (2 downto 0),
);
end component;
constant ADRWIDTH : integer := 8;
......@@ -81,8 +78,7 @@ architecture Behavioral of axi_present_tb is
signal S_AXI_ARPROT : std_logic_vector (2 downto 0) := "010";
signal S_AXI_RDATA : std_logic_vector(31 downto 0) := (others => '0');
signal state_signal : std_logic_vector (2 downto 0);
signal ip_plaintext_signal : std_logic_vector (63 downto 0);
signal ip_plaintext_buffer : std_logic_vector (31 downto 0);
--------------------------------------------------------
constant ClockPeriod : time := 5 ns;
constant ClockPeriod2 : time := 10 ns;
......@@ -115,9 +111,7 @@ begin
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_RDATA => S_AXI_RDATA,
state_signal => state_signal,
ip_plaintext_signal => ip_plaintext_signal,
ip_plaintext_buffer => ip_plaintext_buffer
state_signal => state_signal
--------------------------------------------------------
);
--stimulus :process
......@@ -196,7 +190,7 @@ begin
S_AXI_ARESETN <= '1';
S_AXI_AWADDR <= x"01";
S_AXI_WDATA <= x"deadbeef";
S_AXI_WDATA <= x"00000000";
S_AXI_WSTRB <= b"0000";
sendIt <= '1'; --Start AXI Write to Slave
wait for 1 ns;
......@@ -206,7 +200,7 @@ begin
S_AXI_WSTRB <= b"0000";
S_AXI_AWADDR <= x"01";
S_AXI_WDATA <= x"beefbeef";
S_AXI_WDATA <= x"00000001";
S_AXI_WSTRB <= b"0000";
sendIt <= '1'; --Start AXI Write to Slave
wait for 1 ns;
......@@ -216,7 +210,7 @@ begin
S_AXI_WSTRB <= b"0000";
S_AXI_AWADDR <= x"01";
S_AXI_WDATA <= x"ffffffff";
S_AXI_WDATA <= x"00000002";
S_AXI_WSTRB <= b"1111";
sendIt <= '1'; --Start AXI Write to Slave
wait for 1 ns;
......@@ -226,7 +220,7 @@ begin
S_AXI_WSTRB <= b"0000";
S_AXI_AWADDR <= x"01";
S_AXI_WDATA <= x"32132132";
S_AXI_WDATA <= x"00000002";
S_AXI_WSTRB <= b"1111";
sendIt <= '1'; --Start AXI Write to Slave
wait for 1 ns;
......
......@@ -37,7 +37,9 @@ entity axi_present is
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
state_signal : out std_logic_vector (2 downto 0)
state_signal : out std_logic_vector (2 downto 0);
ip_plaintext_signal : out std_logic_vector (63 downto 0);
ip_plaintext_buffer : out std_logic_vector (31 downto 0)
);
end entity;
architecture behavioral of axi_present is
......@@ -52,12 +54,12 @@ architecture behavioral of axi_present is
ciphertext : out std_logic_vector(63 downto 0)
);
end component;
type text_buffer is array (0 to 1) of std_logic_vector(DATAWIDTH - 1 downto 0);
type text_buffer is array (0 to 1) of std_logic_vector(DATAWIDTH - 1 downto 0) ;
type key_buffer is array (0 to 3) of std_logic_vector(DATAWIDTH - 1 downto 0);
signal plaintext_buf : text_buffer;
signal ciphertext_buf : text_buffer;
signal key_buf : key_buffer;
signal plaintext_buf : text_buffer ;--:= (others => ( others => '0')) ;
signal ciphertext_buf : text_buffer;--:= (others => ( others => '0'));
signal key_buf : key_buffer ;--:= (others => ( others => '0'));
constant plaintext_reads : natural := 2;
constant key_reads : natural := 4;
......@@ -93,8 +95,10 @@ begin
S_AXI_AWREADY <= '1' when (state = read_plaintext or state = read_key) else '0';
S_AXI_RVALID <= '1' when state = write_ciphertext else '0';
S_AXI_ARREADY <= '1' when state = write_ciphertext else '0';
state_machine : process (S_AXI_ACLK)
ip_plaintext_signal <= ip_plaintext;
ip_plaintext_buffer <= plaintext_buf(1);
state_machine : process (S_AXI_ACLK,S_AXI_WDATA,S_AXI_ARESETN,state)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
......@@ -120,6 +124,7 @@ begin
counter <= 0;
else
counter <= counter + 1;
state <= read_plaintext;
end if;
end if;
......@@ -129,6 +134,7 @@ begin
if counter = key_reads - 1 then
state <= stabilize;
counter <= 0;
else
counter <= counter + 1;
end if;
......@@ -194,6 +200,9 @@ begin
S_AXI_BVALID <= '1';
S_AXI_BRESP <= "00";
S_AXI_RRESP <= "00";
else
S_AXI_BVALID <= '0';
end if;
end if;
end process;
......
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