Commit 68ec2b04 authored by tebina nasreddine's avatar tebina nasreddine
Browse files

write test

parent 5b9bd617
......@@ -43,7 +43,10 @@ architecture Behavioral of axi_present_tb is
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
state_signal : out std_logic_vector (2 downto 0),
state_signal : out std_logic_vector (2 downto 0);
ip_plaintext_signal : out std_logic_vector (63 downto 0);
ip_plaintext_buffer : out std_logic_vector (31 downto 0)
);
end component;
......@@ -78,6 +81,9 @@ architecture Behavioral of axi_present_tb is
signal S_AXI_ARPROT : std_logic_vector (2 downto 0) := "010";
signal S_AXI_RDATA : std_logic_vector(31 downto 0) := (others => '0');
signal state_signal : std_logic_vector (2 downto 0);
signal ip_plaintext_signal : std_logic_vector ( 63 downto 0 );
signal ip_plaintext_buffer : std_logic_vector ( 31 downto 0 );
--------------------------------------------------------
constant ClockPeriod : time := 5 ns;
......@@ -111,7 +117,9 @@ begin
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_RDATA => S_AXI_RDATA,
state_signal => state_signal
state_signal => state_signal,
ip_plaintext_signal => ip_plaintext_signal,
ip_plaintext_buffer => ip_plaintext_buffer
--------------------------------------------------------
);
--stimulus :process
......@@ -190,7 +198,7 @@ begin
S_AXI_ARESETN <= '1';
S_AXI_AWADDR <= x"01";
S_AXI_WDATA <= x"00000000";
S_AXI_WDATA <= x"deadbeef";
S_AXI_WSTRB <= b"0000";
sendIt <= '1'; --Start AXI Write to Slave
wait for 1 ns;
......@@ -200,7 +208,7 @@ begin
S_AXI_WSTRB <= b"0000";
S_AXI_AWADDR <= x"01";
S_AXI_WDATA <= x"00000001";
S_AXI_WDATA <= x"deaddead";
S_AXI_WSTRB <= b"0000";
sendIt <= '1'; --Start AXI Write to Slave
wait for 1 ns;
......@@ -210,7 +218,7 @@ begin
S_AXI_WSTRB <= b"0000";
S_AXI_AWADDR <= x"01";
S_AXI_WDATA <= x"00000002";
S_AXI_WDATA <= x"beafbeaf";
S_AXI_WSTRB <= b"1111";
sendIt <= '1'; --Start AXI Write to Slave
wait for 1 ns;
......@@ -220,7 +228,7 @@ begin
S_AXI_WSTRB <= b"0000";
S_AXI_AWADDR <= x"01";
S_AXI_WDATA <= x"00000002";
S_AXI_WDATA <= x"B16B00B5";
S_AXI_WSTRB <= b"1111";
sendIt <= '1'; --Start AXI Write to Slave
wait for 1 ns;
......@@ -230,7 +238,7 @@ begin
S_AXI_WSTRB <= b"0000";
S_AXI_AWADDR <= x"01";
S_AXI_WDATA <= x"00000002";
S_AXI_WDATA <= x"00000000";
S_AXI_WSTRB <= b"1111";
sendIt <= '1'; --Start AXI Write to Slave
wait for 1 ns;
......
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