Commit 75fd08e1 authored by tebina nasreddine's avatar tebina nasreddine
Browse files

constant_key

parent e6e4ad2e
......@@ -53,22 +53,23 @@ architecture behavioral of axi_present is
);
end component;
type text_buffer is array (0 to 5) of std_logic_vector(DATAWIDTH - 1 downto 0) ;
type key_buffer is array (0 to 3) of std_logic_vector(DATAWIDTH - 1 downto 0);
--type key_buffer is array (0 to 3) of std_logic_vector(DATAWIDTH - 1 downto 0);
signal plaintext_buf : text_buffer ;--:= (others => ( others => '0')) ;
signal ciphertext_buf : text_buffer;--:= (others => ( others => '0'));
signal key_buf : key_buffer ;--:= (others => ( others => '0'));
--signal key_buf : key_buffer ;--:= (others => ( others => '0'));
constant key_value : std_logic_vector (127 downto 0) := x"00000000000000000000000000000000";
constant plaintext_reads : natural := 2;
constant key_reads : natural := 4;
--constant key_reads : natural := 4;
constant active_cycles : natural := 33;
constant ciphertext_writes : natural := 2;
signal counter : natural range 0 to 32;
signal ip_plaintext : std_logic_vector(63 downto 0);
signal ip_key : std_logic_vector(127 downto 0);
--signal ip_key : std_logic_vector(127 downto 0);
signal ip_reset : std_logic;
signal ip_ciphertext : std_logic_vector(63 downto 0);
type state_type is (idle, read_plaintext, read_key, stabilize, stabilize_read,active, write_ciphertext);
type state_type is (idle, read_plaintext, stabilize, stabilize_read,active, write_ciphertext);
signal state : state_type;
signal ciphertext_temp_buf : std_logic_vector(DATAWIDTH - 1 downto 0) ;
begin
......@@ -78,15 +79,16 @@ begin
)
port map(
plaintext => ip_plaintext,
key => ip_key,
key => key_value,
clk => S_AXI_ACLK,
reset => ip_reset,
ciphertext => ip_ciphertext
);
ip_plaintext <= plaintext_buf(0) & plaintext_buf(1);
ciphertext_buf (0) <= ip_ciphertext (31 downto 0);
ciphertext_buf (1) <= ip_ciphertext (63 downto 32);
ip_key <= key_buf(0) & key_buf(1) & key_buf(2) & key_buf(3);
--ip_key <= key_value ;
ip_reset <= '0' when state = active else '1';
S_AXI_BRESP <= "00";
S_AXI_RRESP <= "00";
......@@ -121,14 +123,14 @@ begin
state <= stabilize;
end if;
when read_key =>
if S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' then
key_buf(counter-plaintext_reads-1) <= S_AXI_WDATA;
S_AXI_BVALID <= '1';
S_AXI_WREADY <= '1';
S_AXI_AWREADY <= '1' ;
state <= stabilize;
end if;
--when read_key =>
--if S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' then
--key_buf(counter-plaintext_reads-1) <= S_AXI_WDATA;
--S_AXI_BVALID <= '1';
--S_AXI_WREADY <= '1';
--S_AXI_AWREADY <= '1' ;
--state <= stabilize;
--end if;
when stabilize =>
counter <= counter +1;
......@@ -137,7 +139,7 @@ begin
S_AXI_AWREADY <= '0';
case counter is
when 0 to 1 => state <= read_plaintext ;
when 2 to 5 => state <= read_key ;
--when 2 to 5 => state <= read_key ;
when others => state <= active;
counter <= 0 ;
end case;
......
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