Commit 9f86a313 authored by tebina nasreddine's avatar tebina nasreddine
Browse files

write signals working

parent 0bc9d059
......@@ -45,7 +45,12 @@ architecture Behavioral of axi_present_tb is
S_AXI_BREADY : in std_logic;
state_signal : out std_logic_vector (2 downto 0);
ip_plaintext_signal : out std_logic_vector (63 downto 0);
ip_plaintext_buffer : out std_logic_vector (31 downto 0)
ip_plaintext_buffer : out std_logic_vector (31 downto 0);
counter_signal : out natural;
ip_key_signal : out std_logic_vector (127 downto 0);
ip_key_buffer : out std_logic_vector (31 downto 0);
ip_ciphertext_signal : out std_logic_vector (63 downto 0)
);
......@@ -83,8 +88,10 @@ architecture Behavioral of axi_present_tb is
signal state_signal : std_logic_vector (2 downto 0);
signal ip_plaintext_signal : std_logic_vector ( 63 downto 0 );
signal ip_plaintext_buffer : std_logic_vector ( 31 downto 0 );
signal counter_signal : natural ;
signal ip_key_signal : std_logic_vector (127 downto 0);
signal ip_key_buffer : std_logic_vector (31 downto 0);
signal ip_ciphertext_signal : std_logic_vector (63 downto 0);
--------------------------------------------------------
constant ClockPeriod : time := 5 ns;
constant ClockPeriod2 : time := 10 ns;
......@@ -119,7 +126,11 @@ begin
S_AXI_RDATA => S_AXI_RDATA,
state_signal => state_signal,
ip_plaintext_signal => ip_plaintext_signal,
ip_plaintext_buffer => ip_plaintext_buffer
ip_plaintext_buffer => ip_plaintext_buffer,
counter_signal => counter_signal,
ip_key_signal => ip_key_signal,
ip_key_buffer => ip_key_buffer,
ip_ciphertext_signal => ip_ciphertext_signal
--------------------------------------------------------
);
--stimulus :process
......@@ -165,10 +176,11 @@ begin
wait until (S_AXI_AWREADY and S_AXI_WREADY) = '1'; --Client ready to read address/data
S_AXI_BREADY <= '1';
wait until S_AXI_BVALID = '1'; -- Write result valid
--assert S_AXI_BRESP = "00" report "AXI data NOT written" severity failure;
assert S_AXI_BRESP = "00" report "AXI data NOT written" severity failure;
S_AXI_AWVALID <= '0';
S_AXI_WVALID <= '0';
S_AXI_BREADY <= '1';
wait until S_AXI_BVALID = '0'; -- All finished
S_AXI_BREADY <= '0';
end loop;
......
......@@ -39,7 +39,12 @@ entity axi_present is
S_AXI_BREADY : in std_logic;
state_signal : out std_logic_vector (2 downto 0);
ip_plaintext_signal : out std_logic_vector (63 downto 0);
ip_plaintext_buffer : out std_logic_vector (31 downto 0)
ip_plaintext_buffer : out std_logic_vector (31 downto 0);
counter_signal : out natural;
ip_key_signal : out std_logic_vector (127 downto 0);
ip_key_buffer : out std_logic_vector (31 downto 0);
ip_ciphertext_signal : out std_logic_vector (63 downto 0)
);
end entity;
architecture behavioral of axi_present is
......@@ -54,7 +59,7 @@ architecture behavioral of axi_present is
ciphertext : out std_logic_vector(63 downto 0)
);
end component;
type text_buffer is array (0 to 1) of std_logic_vector(DATAWIDTH - 1 downto 0) ;
type text_buffer is array (0 to 5) of std_logic_vector(DATAWIDTH - 1 downto 0) ;
type key_buffer is array (0 to 3) of std_logic_vector(DATAWIDTH - 1 downto 0);
signal plaintext_buf : text_buffer ;--:= (others => ( others => '0')) ;
......@@ -70,7 +75,7 @@ architecture behavioral of axi_present is
signal ip_key : std_logic_vector(127 downto 0);
signal ip_reset : std_logic;
signal ip_ciphertext : std_logic_vector(63 downto 0);
type state_type is (idle, read_plaintext, read_key, stabilize, active, write_ciphertext);
type state_type is (idle, read_plaintext, read_key, stabilize, stabilize_read,active, write_ciphertext);
signal state : state_type;
signal done : boolean := false ;
begin
......@@ -98,6 +103,10 @@ begin
ip_plaintext_signal <= ip_plaintext;
ip_plaintext_buffer <= plaintext_buf(1);
ip_key_signal <= ip_key;
ip_key_buffer <= key_buf(1);
counter_signal <= counter;
ip_ciphertext_signal <= ip_ciphertext;
state_machine : process (S_AXI_ACLK,S_AXI_WDATA,S_AXI_ARESETN,state)
begin
if rising_edge(S_AXI_ACLK) then
......@@ -122,47 +131,67 @@ begin
S_AXI_WREADY <= '1';
S_AXI_AWREADY <= '1' ;
plaintext_buf(counter) <= S_AXI_WDATA;
if counter = plaintext_reads - 1 then
S_AXI_BVALID <= '0';
S_AXI_WREADY <= '0';
S_AXI_AWREADY <= '0' ;
state <= read_key;
counter <= 0;
else
counter <= counter + 1;
state <= read_plaintext;
end if;
state <= stabilize;
--if counter = plaintext_reads - 1 then
--S_AXI_BVALID <= '0';
--S_AXI_WREADY <= '0';
--S_AXI_AWREADY <= '0' ;
--state <= read_key;
--counter <= 0;
--else
--counter <= counter + 1;
--state <= read_plaintext;
--end if;
end if;
when read_key =>
if S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' then
key_buf(counter) <= S_AXI_WDATA;
key_buf(counter-plaintext_reads-1) <= S_AXI_WDATA;
S_AXI_BVALID <= '1';
S_AXI_WREADY <= '1';
S_AXI_AWREADY <= '1' ;
state <= stabilize;
if counter = key_reads - 1 then
state <= active;
S_AXI_BVALID <= '0';
S_AXI_WREADY <= '0';
S_AXI_AWREADY <= '0' ;
counter <= 0;
else
counter <= counter + 1;
end if;
--if counter = key_reads - 1 then
--state <= stabilize;
--S_AXI_BVALID <= '0';
--S_AXI_WREADY <= '0';
--S_AXI_AWREADY <= '0';
--counter <= 0;
--else
--counter <= counter + 1;
--end if;
end if;
when stabilize =>
state <= active;
when stabilize =>
counter <= counter +1;
S_AXI_BVALID <= '0';
S_AXI_WREADY <= '0';
S_AXI_AWREADY <= '0';
S_AXI_RVALID <= '0';
case counter is
when 0 to 1 => state <= read_plaintext ;
when 2 to 5 => state <= read_key ;
when others => state <= active;
counter <= 0 ;
end case;
--state <= active;
--S_AXI_BVALID <= '1';
--S_AXI_WREADY <= '1';
--S_AXI_AWREADY <= '1';
when stabilize_read =>
counter <= counter +1 ;
S_AXI_RVALID <= '0';
S_AXI_ARREADY <= '0';
state <= write_ciphertext;
when active =>
if counter = active_cycles - 1 then
ciphertext_buf(0) <= ip_ciphertext(63 downto 32);
ciphertext_buf(1) <= ip_ciphertext(31 downto 0);
S_AXI_BVALID <= '0';
S_AXI_WREADY <= '0';
S_AXI_AWREADY <= '0' ;
--S_AXI_BVALID <= '0';
--S_AXI_WREADY <= '0';
--S_AXI_AWREADY <= '0' ;
state <= write_ciphertext;
counter <= 0;
else
......@@ -171,15 +200,17 @@ begin
when write_ciphertext =>
S_AXI_RDATA <= ciphertext_buf (counter);
S_AXI_RVALID <= '1';
S_AXI_ARREADY <= '1';
state <= stabilize_read;
if S_AXI_RREADY = '1' then
if counter = ciphertext_writes - 1 then
state <= idle;
counter <= 0;
S_AXI_BVALID <= '0';
S_AXI_WREADY <= '0';
S_AXI_AWREADY <= '0' ;
else
counter <= counter + 1;
--else
-- counter <= counter + 1;
end if;
end if;
end case;
......@@ -203,6 +234,8 @@ begin
state_signal <= "100";
when write_ciphertext =>
state_signal <= "101";
when stabilize_read =>
state_signal <= "110";
when others =>
state_signal <= "XXX";
......@@ -227,4 +260,4 @@ S_AXI_RRESP <= "00";
--end if;
-- end process;
end architecture;
\ No newline at end of file
end architecture;
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