Commit b4d66950 authored by tebina nasreddine's avatar tebina nasreddine
Browse files

all working but read

parent 9f86a313
......@@ -45,7 +45,7 @@ architecture Behavioral of axi_present_tb is
S_AXI_BREADY : in std_logic;
state_signal : out std_logic_vector (2 downto 0);
ip_plaintext_signal : out std_logic_vector (63 downto 0);
ip_plaintext_buffer : out std_logic_vector (31 downto 0);
ip_ciphertext_buffer : out std_logic_vector (31 downto 0);
counter_signal : out natural;
ip_key_signal : out std_logic_vector (127 downto 0);
ip_key_buffer : out std_logic_vector (31 downto 0);
......@@ -87,7 +87,7 @@ architecture Behavioral of axi_present_tb is
signal S_AXI_RDATA : std_logic_vector(31 downto 0) := (others => '0');
signal state_signal : std_logic_vector (2 downto 0);
signal ip_plaintext_signal : std_logic_vector ( 63 downto 0 );
signal ip_plaintext_buffer : std_logic_vector ( 31 downto 0 );
signal ip_ciphertext_buffer : std_logic_vector ( 31 downto 0 );
signal counter_signal : natural ;
signal ip_key_signal : std_logic_vector (127 downto 0);
signal ip_key_buffer : std_logic_vector (31 downto 0);
......@@ -126,7 +126,7 @@ begin
S_AXI_RDATA => S_AXI_RDATA,
state_signal => state_signal,
ip_plaintext_signal => ip_plaintext_signal,
ip_plaintext_buffer => ip_plaintext_buffer,
ip_ciphertext_buffer => ip_ciphertext_buffer,
counter_signal => counter_signal,
ip_key_signal => ip_key_signal,
ip_key_buffer => ip_key_buffer,
......
......@@ -39,7 +39,7 @@ entity axi_present is
S_AXI_BREADY : in std_logic;
state_signal : out std_logic_vector (2 downto 0);
ip_plaintext_signal : out std_logic_vector (63 downto 0);
ip_plaintext_buffer : out std_logic_vector (31 downto 0);
ip_ciphertext_buffer : out std_logic_vector (31 downto 0);
counter_signal : out natural;
ip_key_signal : out std_logic_vector (127 downto 0);
ip_key_buffer : out std_logic_vector (31 downto 0);
......@@ -95,19 +95,17 @@ begin
ciphertext_buf (0) <= ip_ciphertext (31 downto 0);
ciphertext_buf (1) <= ip_ciphertext (63 downto 32);
ip_key <= key_buf(0) & key_buf(1) & key_buf(2) & key_buf(3);
ip_reset <= '1' when state = active else '0';
--S_AXI_WREADY <= '1' when (state = read_plaintext or state = read_key) else '0';
--S_AXI_AWREADY <= '1' when (state = read_plaintext or state = read_key) else '0';
S_AXI_RVALID <= '1' when state = write_ciphertext else '0';
S_AXI_ARREADY <= '1' when state = write_ciphertext else '0';
ip_reset <= '0' when state = active else '1';
S_AXI_BRESP <= "00";
S_AXI_RRESP <= "00";
ip_plaintext_signal <= ip_plaintext;
ip_plaintext_buffer <= plaintext_buf(1);
ip_ciphertext_buffer <= ciphertext_buf(0);
ip_key_signal <= ip_key;
ip_key_buffer <= key_buf(1);
counter_signal <= counter;
ip_ciphertext_signal <= ip_ciphertext;
state_machine : process (S_AXI_ACLK,S_AXI_WDATA,S_AXI_ARESETN,state)
state_machine : process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
......@@ -116,10 +114,12 @@ begin
else
case state is
when idle =>
ciphertext_buf(0) <= (others => '0');
ciphertext_buf(1) <= (others => '0');
S_AXI_RDATA <= (others => '0');
S_AXI_RVALID <= '0';
S_AXI_ARREADY <= '0';
S_AXI_BVALID <= '0';
S_AXI_WREADY <= '0';
S_AXI_AWREADY <= '0' ;
if S_AXI_WVALID = '1' then
state <= read_plaintext;
counter <= 0;
......@@ -132,16 +132,6 @@ begin
S_AXI_AWREADY <= '1' ;
plaintext_buf(counter) <= S_AXI_WDATA;
state <= stabilize;
--if counter = plaintext_reads - 1 then
--S_AXI_BVALID <= '0';
--S_AXI_WREADY <= '0';
--S_AXI_AWREADY <= '0' ;
--state <= read_key;
--counter <= 0;
--else
--counter <= counter + 1;
--state <= read_plaintext;
--end if;
end if;
when read_key =>
......@@ -151,16 +141,6 @@ begin
S_AXI_WREADY <= '1';
S_AXI_AWREADY <= '1' ;
state <= stabilize;
--if counter = key_reads - 1 then
--state <= stabilize;
--S_AXI_BVALID <= '0';
--S_AXI_WREADY <= '0';
--S_AXI_AWREADY <= '0';
--counter <= 0;
--else
--counter <= counter + 1;
--end if;
end if;
when stabilize =>
......@@ -168,30 +148,22 @@ begin
S_AXI_BVALID <= '0';
S_AXI_WREADY <= '0';
S_AXI_AWREADY <= '0';
S_AXI_RVALID <= '0';
case counter is
when 0 to 1 => state <= read_plaintext ;
when 2 to 5 => state <= read_key ;
when others => state <= active;
counter <= 0 ;
end case;
--state <= active;
--S_AXI_BVALID <= '1';
--S_AXI_WREADY <= '1';
--S_AXI_AWREADY <= '1';
when stabilize_read =>
counter <= counter +1 ;
S_AXI_RVALID <= '0';
S_AXI_ARREADY <= '0';
state <= write_ciphertext;
if counter = ciphertext_writes-1 then
state <= idle ;
end if;
when active =>
if counter = active_cycles - 1 then
ciphertext_buf(0) <= ip_ciphertext(63 downto 32);
ciphertext_buf(1) <= ip_ciphertext(31 downto 0);
--S_AXI_BVALID <= '0';
--S_AXI_WREADY <= '0';
--S_AXI_AWREADY <= '0' ;
state <= write_ciphertext;
counter <= 0;
else
......@@ -199,20 +171,12 @@ begin
end if;
when write_ciphertext =>
S_AXI_RDATA <= ciphertext_buf (counter);
--if S_AXI_ARVALID = '1' and S_AXI_RREADY = '1' then
S_AXI_RDATA <= ciphertext_buf(counter);
S_AXI_RVALID <= '1';
S_AXI_ARREADY <= '1';
state <= stabilize_read;
if S_AXI_RREADY = '1' then
if counter = ciphertext_writes - 1 then
state <= idle;
counter <= 0;
--else
-- counter <= counter + 1;
end if;
end if;
--end if ;
end case;
end if;
end if;
......@@ -241,23 +205,5 @@ begin
end case;
end process;
S_AXI_BRESP <= "00";
S_AXI_RRESP <= "00";
-- process (S_AXI_ACLK)
-- begin
-- if S_AXI_ARESETN = '0' then
---- S_AXI_BVALID <= '0';
--else if (S_AXI_WVALID ='1') then
-- S_AXI_BRESP <= "00";
-- S_AXI_RRESP <= "00";
-- if done = true then
-- S_AXI_BVALID <= '1';
--else
--S_AXI_BVALID <= '0';
--end if ;
---end if;
--end if;
-- end process;
end architecture;
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