Commit d5cefa94 authored by tebina nasreddine's avatar tebina nasreddine
Browse files

Read working

parent b4d66950
......@@ -282,13 +282,13 @@ begin
S_AXI_ARADDR <= "00000000";
readIt <= '1'; --Start AXI Read from Slave
wait for 5 ns;
wait for 1 ns;
readIt <= '0'; --Clear "Start Read" Flag
wait until S_AXI_RVALID = '1';
wait until S_AXI_RVALID = '0';
S_AXI_ARADDR <= "00000010";
readIt <= '1'; --Start AXI Read from Slave
wait for 5 ns;
wait for 1 ns;
readIt <= '0'; --Clear "Start Read" Flag
wait until S_AXI_RVALID = '1';
wait until S_AXI_RVALID = '0';
......
......@@ -78,6 +78,7 @@ architecture behavioral of axi_present is
type state_type is (idle, read_plaintext, read_key, stabilize, stabilize_read,active, write_ciphertext);
signal state : state_type;
signal done : boolean := false ;
signal ciphertext_temp_buf : std_logic_vector(DATAWIDTH - 1 downto 0);
begin
BLOCK_CIPHER : present_top
generic map(
......@@ -164,7 +165,11 @@ begin
end if;
when active =>
if counter = active_cycles - 1 then
state <= write_ciphertext;
S_AXI_RDATA <= ciphertext_buf(0);
ciphertext_temp_buf <= ciphertext_buf(1);
S_AXI_RVALID <= '1';
S_AXI_ARREADY <= '1';
state <= stabilize_read;
counter <= 0;
else
counter <= counter + 1;
......@@ -172,7 +177,7 @@ begin
when write_ciphertext =>
--if S_AXI_ARVALID = '1' and S_AXI_RREADY = '1' then
S_AXI_RDATA <= ciphertext_buf(counter);
S_AXI_RDATA <= ciphertext_temp_buf;
S_AXI_RVALID <= '1';
S_AXI_ARREADY <= '1';
state <= stabilize_read;
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment