Read working

src/axi_present.vhd

@@ -97,8 +97,8 @@ begin
 			ciphertext_buf (1) <= ip_ciphertext (63 downto 32);
 			ip_key <= key_buf(0) & key_buf(1) & key_buf(2) & key_buf(3);
 			ip_reset <= '0' when state = active else '1';
-			--S_AXI_BRESP <= "00";
-            --S_AXI_RRESP <= "00";
+			S_AXI_BRESP <= "00";
+            S_AXI_RRESP <= "00";
 			ip_plaintext_signal <= ip_plaintext;
 			ip_ciphertext_buffer <= ciphertext_buf(0);
 			ip_key_signal <= ip_key;
@@ -108,14 +108,6 @@ begin
 			
 			state_machine : process (S_AXI_ACLK)
 			begin
-				S_AXI_BVALID  <= '0';
-				S_AXI_BRESP   <= (others => '0');
-				S_AXI_ARREADY <= '0';
-				S_AXI_RVALID  <= '0';
-				S_AXI_RDATA   <= (others => '0');
-				S_AXI_RRESP   <= (others => '0');
-				S_AXI_AWREADY <= '0';
-				S_AXI_WREADY  <= '0';
 				if rising_edge(S_AXI_ACLK) then
 					if S_AXI_ARESETN = '0' then
 						state <= idle;
@@ -124,8 +116,8 @@ begin
 						case state is
 							when idle => 
 								S_AXI_RDATA <= (others => '0');
-								--S_AXI_RVALID <= '0';
-                                --S_AXI_ARREADY <= '0';
+								S_AXI_RVALID <= '0';
+                                S_AXI_ARREADY <= '0';
                                 S_AXI_BVALID <= '0';
 								S_AXI_WREADY <= '0';
 								S_AXI_AWREADY <= '0' ;
@@ -165,25 +157,19 @@ begin
 							     end case;
                             when stabilize_read => 
                                 counter <= counter +1 ;
-                                --S_AXI_RVALID <= '0';
-                                --S_AXI_ARREADY <= '0';
+                                S_AXI_RVALID <= '0';
+                                S_AXI_ARREADY <= '0';
                                 state <= write_ciphertext;
                                 if counter = ciphertext_writes-1  then 
                                 state <= idle ;
                                 end if;
 							when active => 
 								if counter = active_cycles - 1 then
-<<<<<<< HEAD
 								S_AXI_RDATA <= ciphertext_buf(0);
 								ciphertext_temp_buf <= ciphertext_buf(1);
 						        S_AXI_RVALID <= '1';									
                                 S_AXI_ARREADY <= '1';
 									state <= stabilize_read;
-=======
-									S_AXI_ARREADY <= '1';
-									S_AXI_RVALID <= '1';
-									state <= write_ciphertext;
->>>>>>> 13f8c5afba85fb493c7aca0d2f05f461299239b7
 									counter <= 0;									
 								else
 									counter <= counter + 1;
@@ -191,16 +177,9 @@ begin
  
 							when write_ciphertext => 
 								--if S_AXI_ARVALID = '1' and S_AXI_RREADY = '1' then 
-<<<<<<< HEAD
 								S_AXI_RDATA <= ciphertext_temp_buf;
 						        S_AXI_RVALID <= '1';									
                                 S_AXI_ARREADY <= '1';
-=======
-								S_AXI_RDATA <= ciphertext_buf(counter);
-								S_AXI_ARREADY <= '0';
-						        S_AXI_RVALID <= '0';									
-                                --S_AXI_ARREADY <= '0';
->>>>>>> 13f8c5afba85fb493c7aca0d2f05f461299239b7
                                 state <= stabilize_read;
                                 --end if ;
 						end case;
@@ -209,7 +188,6 @@ begin
 			end process;
  
 
-
 			process (state)
 				begin
 					case state is