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Commit e6e4ad2e authored by tebina nasreddine's avatar tebina nasreddine
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Cleanup

parent e52f6a18
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sim/axi_present_tb.vhd
View file @ e6e4ad2e
......@@ -42,14 +42,7 @@ architecture Behavioral of axi_present_tb is
-- Write Response Channel
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
state_signal : out std_logic_vector (2 downto 0);
ip_plaintext_signal : out std_logic_vector (63 downto 0);
ip_ciphertext_buffer : out std_logic_vector (31 downto 0);
counter_signal : out natural;
ip_key_signal : out std_logic_vector (127 downto 0);
ip_key_buffer : out std_logic_vector (31 downto 0);
ip_ciphertext_signal : out std_logic_vector (63 downto 0)
S_AXI_BREADY : in std_logic
......@@ -85,13 +78,7 @@ architecture Behavioral of axi_present_tb is
signal S_AXI_AWPROT : std_logic_vector (2 downto 0) := "010";
signal S_AXI_ARPROT : std_logic_vector (2 downto 0) := "010";
signal S_AXI_RDATA : std_logic_vector(31 downto 0) := (others => '0');
signal state_signal : std_logic_vector (2 downto 0);
signal ip_plaintext_signal : std_logic_vector ( 63 downto 0 );
signal ip_ciphertext_buffer : std_logic_vector ( 31 downto 0 );
signal counter_signal : natural ;
signal ip_key_signal : std_logic_vector (127 downto 0);
signal ip_key_buffer : std_logic_vector (31 downto 0);
signal ip_ciphertext_signal : std_logic_vector (63 downto 0);
--------------------------------------------------------
constant ClockPeriod : time := 5 ns;
constant ClockPeriod2 : time := 10 ns;
......@@ -123,14 +110,7 @@ begin
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_RDATA => S_AXI_RDATA,
state_signal => state_signal,
ip_plaintext_signal => ip_plaintext_signal,
ip_ciphertext_buffer => ip_ciphertext_buffer,
counter_signal => counter_signal,
ip_key_signal => ip_key_signal,
ip_key_buffer => ip_key_buffer,
ip_ciphertext_signal => ip_ciphertext_signal
S_AXI_RDATA => S_AXI_RDATA
--------------------------------------------------------
);
--stimulus :process
......@@ -292,7 +272,92 @@ begin
readIt <= '0'; --Clear "Start Read" Flag
wait until S_AXI_RVALID = '1';
wait until S_AXI_RVALID = '0';
------------------
------------------
S_AXI_AWADDR <= x"01";
S_AXI_WDATA <= x"deadbeef";
S_AXI_WSTRB <= b"0000";
sendIt <= '1'; --Start AXI Write to Slave
wait for 1 ns;
sendIt <= '0'; --Clear Start Send Flag
wait until S_AXI_BVALID = '1';
wait until S_AXI_BVALID = '0'; --AXI Write finished
S_AXI_WSTRB <= b"0000";
S_AXI_AWADDR <= x"01";
S_AXI_WDATA <= x"deaddead";
S_AXI_WSTRB <= b"0000";
sendIt <= '1'; --Start AXI Write to Slave
wait for 1 ns;
sendIt <= '0'; --Clear Start Send Flag
wait until S_AXI_BVALID = '1';
wait until S_AXI_BVALID = '0'; --AXI Write finished
S_AXI_WSTRB <= b"0000";
S_AXI_AWADDR <= x"01";
S_AXI_WDATA <= x"beafbeaf";
S_AXI_WSTRB <= b"1111";
sendIt <= '1'; --Start AXI Write to Slave
wait for 1 ns;
sendIt <= '0'; --Clear Start Send Flag
wait until S_AXI_BVALID = '1';
wait until S_AXI_BVALID = '0'; --AXI Write finished
S_AXI_WSTRB <= b"0000";
S_AXI_AWADDR <= x"01";
S_AXI_WDATA <= x"00000000";
S_AXI_WSTRB <= b"1111";
sendIt <= '1'; --Start AXI Write to Slave
wait for 1 ns;
sendIt <= '0'; --Clear Start Send Flag
wait until S_AXI_BVALID = '1';
wait until S_AXI_BVALID = '0'; --AXI Write finished
S_AXI_WSTRB <= b"0000";
S_AXI_AWADDR <= x"01";
S_AXI_WDATA <= x"00000000";
S_AXI_WSTRB <= b"1111";
sendIt <= '1'; --Start AXI Write to Slave
wait for 1 ns;
sendIt <= '0'; --Clear Start Send Flag
wait until S_AXI_BVALID = '1';
wait until S_AXI_BVALID = '0'; --AXI Write finished
S_AXI_WSTRB <= b"0000";
S_AXI_AWADDR <= x"04";
S_AXI_WDATA <= x"00000000";
S_AXI_WSTRB <= b"1111";
sendIt <= '1'; --Start AXI Write to Slave
wait for 1 ns;
sendIt <= '0'; --Clear Start Send Flag
wait until S_AXI_BVALID = '1';
wait until S_AXI_BVALID = '0'; --AXI Write finished
S_AXI_WSTRB <= b"0000";
S_AXI_AWADDR <= x"04";
S_AXI_WDATA <= x"A5A5A5A5";
S_AXI_WSTRB <= b"1111";
sendIt <= '1'; --Start AXI Write to Slave
wait for 1 ns;
sendIt <= '0'; --Clear Start Send Flag
wait until S_AXI_BVALID = '1';
wait until S_AXI_BVALID = '0'; --AXI Write finished
S_AXI_WSTRB <= b"0000";
S_AXI_ARADDR <= "00000000";
readIt <= '1'; --Start AXI Read from Slave
wait for 1 ns;
readIt <= '0'; --Clear "Start Read" Flag
wait until S_AXI_RVALID = '1';
wait until S_AXI_RVALID = '0';
S_AXI_ARADDR <= "00000010";
readIt <= '1'; --Start AXI Read from Slave
wait for 1 ns;
readIt <= '0'; --Clear "Start Read" Flag
wait until S_AXI_RVALID = '1';
wait until S_AXI_RVALID = '0';
wait; -- will wait forever
end process tb;
......
src/axi_present.vhd
View file @ e6e4ad2e
......@@ -36,14 +36,7 @@ entity axi_present is
-- Write Response Channel
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
state_signal : out std_logic_vector (2 downto 0);
ip_plaintext_signal : out std_logic_vector (63 downto 0);
ip_ciphertext_buffer : out std_logic_vector (31 downto 0);
counter_signal : out natural;
ip_key_signal : out std_logic_vector (127 downto 0);
ip_key_buffer : out std_logic_vector (31 downto 0);
ip_ciphertext_signal : out std_logic_vector (63 downto 0)
S_AXI_BREADY : in std_logic
);
end entity;
......@@ -77,8 +70,7 @@ architecture behavioral of axi_present is
signal ip_ciphertext : std_logic_vector(63 downto 0);
type state_type is (idle, read_plaintext, read_key, stabilize, stabilize_read,active, write_ciphertext);
signal state : state_type;
signal done : boolean := false ;
signal ciphertext_temp_buf : std_logic_vector(DATAWIDTH - 1 downto 0);
signal ciphertext_temp_buf : std_logic_vector(DATAWIDTH - 1 downto 0) ;
begin
BLOCK_CIPHER : present_top
generic map(
......@@ -91,7 +83,6 @@ begin
reset => ip_reset,
ciphertext => ip_ciphertext
);
ip_plaintext <= plaintext_buf(0) & plaintext_buf(1);
ciphertext_buf (0) <= ip_ciphertext (31 downto 0);
ciphertext_buf (1) <= ip_ciphertext (63 downto 32);
......@@ -99,12 +90,7 @@ begin
ip_reset <= '0' when state = active else '1';
S_AXI_BRESP <= "00";
S_AXI_RRESP <= "00";
ip_plaintext_signal <= ip_plaintext;
ip_ciphertext_buffer <= ciphertext_buf(0);
ip_key_signal <= ip_key;
ip_key_buffer <= key_buf(1);
counter_signal <= counter;
ip_ciphertext_signal <= ip_ciphertext;
state_machine : process (S_AXI_ACLK)
begin
......@@ -188,27 +174,5 @@ begin
end process;
process (state)
begin
case state is
when idle =>
state_signal <= "000";
when read_plaintext =>
state_signal <= "001";
when read_key =>
state_signal <= "010";
when stabilize =>
state_signal <= "011";
when active =>
state_signal <= "100";
when write_ciphertext =>
state_signal <= "101";
when stabilize_read =>
state_signal <= "110";
when others =>
state_signal <= "XXX";
end case;
end process;
end architecture;
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